1. Field of the Invention
This invention relates to a phase compensation circuit, and a power circuit having it. More specifically, the invention relates to those useful when applied to a power circuit for making phase compensation for a feedback system using an error amplifier, such as a DC-DC converter.
2. Description of the Related Art
FIG. 1 is a block diagram showing the whole of a step-down DC-DC converter, which is one of representative power circuits. As shown in the drawing, an error amplifier 1 makes a comparison between a reference voltage VREF, which represents a preset voltage value, and a feedback signal FB, and delivers an error signal S1 which represents a deviation between VREF and FB. The feedback signal FB is obtained by dividing an output voltage VOUT by feedback resistances Rf1 and Rf2.
A comparator 2 compares the error signal S1 with an output signal S2 of a circuit 3, which generates a triangular wave, and sends out a duty signal S3 representing a duty ratio which determines the value of the output voltage VOUT of the DC-DC converter, namely, an output voltage value. The duty signal S3 controls the ON-OFF times of a P-channel MOS transistor P1 and an N-channel MOS transistor N1 via an output buffer circuit 6. This control defines the value of the output voltage VOUT based on an input voltage VIN. A reactance L0 and a capacitor C0 function to smooth the output voltage VOUT.
In such a feedback system using the error amplifier 1, a phase compensation circuit 7 is usually present for making phase compensation.
A concrete configurational example of the phase compensation circuit 7 concerned with prior art is shown in FIG. 2. As shown in this drawing, the phase compensation circuit 7 consists of a resistance R1 and a capacitor C connected in series, and is connected to the output side of the error amplifier 1. FIG. 3 is a Bode's diagram in this case.
In the case of the DC-DC converter, management of a gain Az of the circuit shown in FIG. 2 is very important. That is, a zero point (a point at which the phase returns by 45 degrees; a frequency at this point is taken as a zero-point frequency fz (in the vicinity of 5 KHz in FIG. 3)) for phase compensation is created by the capacitor C and the resistance R1 of the phase compensation circuit 7, as shown in FIG. 3, to return the phase. In the region of several hundred Hz to several hundred kHz, a lag in the phase based on the reactance L0 and capacitor C0 for smoothing normally occurs. If the gain Az is large in this region, therefore, oscillations are apt to take place, inducing instability of actions. If the gain Az is too small, on the other hand, response characteristics deteriorate. Hence, it is of vital importance to control the value of the gain Az, especially, the value in the above-mentioned region, to a predetermined range with high accuracy.
The gain Az can be calculated as follows:Az=gm1×R1  (1)where gm1 denotes the transconductance of the error amplifier 1, and R1 denotes the resistance value of the resistance R1.
The larger the value of the transconductance gm1, the greater the total gain of the error amplifier 1, and the better the output voltage accuracy and the load regulation become.
If the transconductance gm1 is increased, with the gain Az being controlled to a certain value (e.g., 14 dB), the resistance value R1 is naturally decreased as seen from the equation (1).
Moreover, the zero point for phase compensation for the certain frequency is created by the capacitor C and the resistance R1. Let the frequency for this zero point (the point at which the phase returns by 45 degrees) be fz. In this case, the zero-point frequency fz can be calculated as follows:fz=1/(2×π×C×R1)  (2)
Hence, if the value of the transconductance gm1 is increased, and the resistance R1 is decreased, then the capacitor C has to be rendered great in order to create the zero-point frequency fz at a certain fixed point. This poses an areal problem encountered when arranging the capacitor C on a silicon substrate, namely, the problem that the footprint of the capacitor C (namely, an area occupied by the capacitor C) on an IC chip is large.
There is U.S. Pat. No. 5,382,918 as a document which discloses a technology for decreasing the area occupied by the capacitor for phase compensation. This technology is shown in FIG. 4. As shown in this drawing, a phase compensation circuit 01 is connected to the side of an output terminal 03 of an error amplifier 02, which is a gm Amp, to create a zero point, thereby increasing a phase margin. The phase compensation circuit 01 is to be basically composed of a resistance 04 and a capacitor 05 connected in series. However, the function of the capacitor 05 is taken up by an operational amplifier 06, whereby the capacitor 05 is removed to decrease the footprint of the phase compensation circuit 01 as compared with the use of the capacitor 05.
The use of the capacitance value of-electrostatic capacity or capacitance after AC conversion is already available as one of techniques on a GIC (generalized impedance converter) circuit (see, for example, Transistor Technology SPECIAL No. 44, Special Issue, Design of Filters, pp. 100-103).
Therefore, the following documents can be named as documents on publicly known technologies relevant to the present invention:
U.S. Pat. No. 5,382,918 (Patent Document 1)
Transistor Technology SPECIAL No. 44, Special Issue, Design of Filters, pp. 100-103 (Non-patent Document 1)
As stated above, when phase compensation is to be made for a feedback system using an error amplifier, such as a DC-DC converter, the capacitance value of the capacitor C used is never low if the actual layout is considered. In some cases, the capacitance value has become a factor imposing restrictions on the characteristics of IC owing to the layout area.